revision 0.0 cmos sram may 2000 k6f1016s4b family - 1 - preliminary the attached datasheets are provided by samsung electronics. samsung electronics co., ltd. reserve the right to change the speci fications and products. samsung electronics will answer to your questions about device. if you have any questions, please contact the samsung branch offices. document title 64k x16 bit super low power and low voltage full cmos static ram revision history revision no. 0.0 remark preliminary history initial draft draft date may 8, 2000
revision 0.0 cmos sram may 2000 k6f1016s4b family - 2 - preliminary product family 1. the parameter is measured with 30pf test load. product family operating temperature vcc range speed power dissipation pkg type standby (i sb1 , typ.) operating (i cc1 , max) k6f1016s4b-f industrial(-40~85 c) 2.3~2.7v 70 1) /85ns 0.5 m a 3ma 48-fbga-6.00x7.00 64k x 16 bit super low power and low voltage full cmos static ram general description the k6f1016s4b families are fabricated by samsung s advanced full cmos process technology. the families support industrial temperature range and 48 ball chip scale package for user flexibility of system design. the families also support low data retention voltage for battery back-up operation with low data retention current. features process technology: full cmos organization: 64k x16 bit power supply voltage: 2.3~2.7v low data retention voltage: 1.5v(min) three state output status and ttl compatible package type: 48-fbga-6.00x7.00 pin description functional block diagram 48-csp - top view lb oe a0 a1 a2 dnu i/o9 ub a3 a4 cs i/o1 i/o10 i/o11 a5 a6 i/o2 i/o3 vss i/o12 dnu a7 i/o4 vcc vcc i/o13 dnu dnu i/o5 vss i/o15 i/o14 a14 a15 i/o6 i/o7 i/o16 dnu a12 a13 we i/o8 dnu a8 a9 a10 a11 dnu 1 2 3 4 5 6 a b c d e f g h samsung electronics co., ltd. reserves the right to change products and specifications without notice . name function name function cs chip select input vcc power oe output enable input vss ground we write enable input ub upper byte(i/o 9 ~ 16 ) a 0 ~a 15 address inputs lb lower byte(i/o 1 ~ 8 ) i/o 1 ~i/o 16 data inputs/outputs dnu do not use precharge circuit. memory array 1024 rows 64 16 columns i/o circuit column select clk gen. row select we oe ub cs i/o 1 ~i/o 8 data cont data cont data cont lb i/o 9 ~i/o 16 vcc vss row addresses control logic column addresses
revision 0.0 cmos sram may 2000 k6f1016s4b family - 3 - preliminary absolute maximum ratings 1) 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. functional oper ation should be restricted to recommended operating condition. exposure to absolute maximum rating conditions for extended periods may affect r eliability. item symbol ratings unit voltage on any pin relative to vss v in , v out -0.2 to v cc +0.3v v voltage on vcc supply relative to vss v cc -0.2 to 3.6v v power dissipation p d 1.0 w storage temperature t stg -65 to 150 c operating temperature t a -40 to 85 c functional description 1. x means don t care. (must be low or high state) cs oe we lb ub i/o 1~8 i/o 9~16 mode power h x 1) x 1) x 1) x 1) high-z high-z deselected standby x 1) x 1) x 1) h h high-z high-z deselected standby l h h l x 1) high-z high-z output disabled active l h h x 1) l high-z high-z output disabled active l l h l h dout high-z lower byte read active l l h h l high-z dout upper byte read active l l h l l dout dout word read active l x 1) l l h din high-z lower byte write active l x 1) l h l high-z din upper byte write active l x 1) l l l din din word write active product list industrial temperature products(-40~85 c) part name function k6f1016s4b-ff70 K6F1016S4B-FF85 48-fbga, 70ns, 2.5v 48-fbga, 85ns, 2.5v
revision 0.0 cmos sram may 2000 k6f1016s4b family - 4 - preliminary dc and operating characteristics 1. super low power product=1 m a with special handling. item symbol test conditions min typ max unit input leakage current i li v in =vss to vcc -1 - 1 m a output leakage current i lo cs =v ih or oe =v ih or we =v il , v io =vss to vcc -1 - 1 m a operating power supply current i cc i io =0ma, cs =v il , v in =v ih or v il - - 2 ma average operating current i cc1 cycle time=1 m s, 100% duty, i io =0ma, cs 0.2v, v in 0.2v or v in 3 v cc - 0.2v - - 3 ma i cc2 cycle time=min, i io =0ma , 100% duty, cs =v il, v in =v ih or v il - - 25 ma output low voltage v ol i ol =0.5ma - - 0.4 v output high voltage v oh i oh =-0.5ma 2.0 - - v standby current(ttl) i sb cs =v ih or lb = ub =v ih , other inputs=v ih or v il - - 0.3 ma standby current (cmos) i sb1 cs 3 vcc-0.2v or lb = ub 3 vcc- 0.2v, cs 0.2v, other inpu ts=0~vcc - 0.5 3 1) m a recommended dc operating conditions 1) note : 1. t a =-40 to 85 c, otherwise specified. 2. overshoot: vcc+1.0v in case of pulse width 20ns. 3. undershoot: -1.0v in case of pulse width 20ns. 4. overshoot and undershoot are sampled, not 100% tested. item symbol min typ max unit supply voltage vcc 2.3 2.5 2.7 v ground vss 0 0 0 v input high voltage v ih 2.0 - vcc+0.2 2) v input low voltage v il -0.2 3) - 0.6 v capacitance 1) (f=1mhz, t a =25 c) 1. capacitance is sampled, not 100% tested item symbol test condition min max unit input capacitance c in v in =0v - 8 pf input/output capacitance c io v io =0v - 10 pf
revision 0.0 cmos sram may 2000 k6f1016s4b family - 5 - preliminary ac characteristics (vcc=2.3~2.7v, industrial product:t a =-40 to 85 c) 1. the parameter is measured with 30pf test load. parameter list symbol speed bins units 70ns 1) 85ns min max min max read read cycle time t rc 70 - 85 - ns address access time t aa - 70 - 85 ns chip select to output t co - 70 - 85 ns output enable to valid output t oe - 35 - 40 ns ub , lb access time t ba - 70 - 85 ns chip select to low-z output t lz 10 - 10 - ns ub , lb enable to low-z output t blz 10 - 10 - ns output enable to low-z output t olz 5 - 5 - ns chip disable to high-z output t hz 0 25 0 25 ns ub , lb disable to high-z output t bhz 0 25 0 25 ns output disable to high-z output t ohz 0 25 0 25 ns output hold from address change t oh 10 - 10 - ns write write cycle time t wc 70 - 85 - ns chip select to end of write t cw 60 - 70 - ns address set-up time t as 0 - 0 - ns address valid to end of write t aw 60 - 70 - ns ub , lb valid to end of write t bw 60 - 70 - ns write pulse width t wp 50 - 60 - ns write recovery time t wr 0 - 0 - ns write to output high-z t whz 0 20 0 25 ns data to write time overlap t dw 30 - 35 - ns data hold from write time t dh 0 - 0 - ns end write to output low-z t ow 5 - 5 - ns data retention characteristics 1. cs 3 vcc-0.2v( cs controlled) or lb = ub 3 vcc-0.2v, cs 0.2v( lb , ub controlled) item symbol test condition min typ max unit vcc for data retention vdr cs 3 vcc-0.2v 1) 1.5 - 2.7 v data retention current idr vcc= 1.5v, cs 3 vcc-0.2v 1) - - 0.5 m a data retention set-up time tsdr see data retention waveform 0 - - ns recovery time trdr trc - - ac operating conditions test conditions (test load and input/output reference) input pulse level: 0.4 to 2.2v input rising and falling time: 5ns input and output reference voltage: 1.1v output load (see right) :c l = 100pf+1ttl c l =30pf+1ttl c l 1) 1. including scope and jig capacitance r 2 2) r 1 2) v tm 3) 2. r 1 =3070 w , r 2 =3150 w 3. v tm =2.3v
revision 0.0 cmos sram may 2000 k6f1016s4b family - 6 - preliminary address data out previous data valid data valid timming diagrams timing waveform of read cycle(1) (address controlled , cs = oe =v il , we =v ih , ub or/and lb =v il ) timing waveform of read cycle(2) ( we =v ih ) data valid high-z t rc cs address ub , lb oe data out t aa t rc t oh t oh t aa t co t ba t oe t olz t blz t lz t ohz t bhz t hz notes ( read cycle) 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection.
revision 0.0 cmos sram may 2000 k6f1016s4b family - 7 - preliminary timing waveform of write cycle(1) ( we controlled) address cs data undefined ub , lb we data in data out timing waveform of write cycle(2) ( cs controlled) address cs data valid ub , lb we data in data out high-z high-z t wc t cw(2) t wr(4) t aw t bw t wp(1) t as(3) t dh t dw t whz t ow t wc t cw(2) t aw t bw t wp(1) t dh t dw t wr(4) high-z high-z data valid t as(3)
revision 0.0 cmos sram may 2000 k6f1016s4b family - 8 - preliminary address cs data valid ub , lb we data in data out high-z high-z timing waveform of write cycle(3) ( ub , lb controlled) notes (write cycle) 1. a wri t e occurs during the overlap(t wp ) of low cs and low we . a write begins when cs goes low and we goes low with asserting ub or lb for single byte operation or simultaneously asserting ub and lb for double byte operation. a write ends at the earliest transi- tion when cs goes high and we goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs going low to end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end or write to the address change. t wr applied in case a write ends as cs or we going high. t wc t cw(2) t bw t wp(1) t dh t dw t wr(4) t aw data retention wave form v cc 2.3v 2.0v v dr cs , lb / ub gnd t as(3) data retention mode cs 3 v cc - 0.2v or lb = ub 3 vcc-0.2v t sdr t rdr
revision 0.0 cmos sram may 2000 k6f1016s4b family - 9 - preliminary c 1 / 2 package dimension 6 5 4 3 2 1 a b c d e f g h c b/2 b c 1 b c bottom view top view d e 2 e 1 e c side view 0 . 8 5 / t y p . 0 . 2 5 / t y p . a y detail a min typ max a - 0.75 - b 5.90 6.00 6.10 b1 - 3.75 - c 6.90 7.00 7.10 c1 - 5.25 - d 0.30 0.35 0.40 e - 1.10 1.20 e1 - 0.85 - e2 0.20 0.25 0.30 y - - 0.08 0.50 0.50 b1 #a1 0 . 3 0 a1 index mark notes. 1. bump counts: 48(8row x 6column) 2. bump pitch : (x,y)=(0.75 x 0.75)(typ.) 3. all tolerence are +/-0.050 unless otherwise specified. 4. typ : typical 5. y is coplanarity: 0.08(max) unit: millimeters 48 ball fine pitch bga(0.75mm ball pitch)
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